Microdevices, such as integrated microcircuits and microelectromechanical systems (MEMS), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microdevices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microdevice fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected or the design is otherwise improved.
Several steps are common to most design flows for integrated microcircuits. Initially, a specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as Verilog or Very high speed integrated circuit Hardware Design Language (VHDL).
The logic of the circuit can be analyzed to confirm that it will accurately perform the functions desired for the circuit, sometimes referred to as “functional verification.” For example, the analysis can include simulating of the logical design, which can show how the logical design responses to transactions or sets of test vectors, for example, generated by a test bench during simulation. Functional verification can include verifying, from the results of the simulation, that the logical design can accurately perform functions for many different aspects of the circuit.
As circuits and their corresponding logical designs become more complex, the task of functional verification becomes increasingly difficult to manage and accomplish. For example, this complexity can include logical designs including multiple power domains, multiple clock domain, multiple different types of resets having various characteristics, or the like. Given the complexity of modern reset functionality in the logical designs, many “bugs” or design flaws are often left unexposed by conventional simulation, leaving system designers unable to adequately verify whether the logical design can properly reset components in the logical design.